The present invention relates to a delay circuit and a delay locked loop (DLL) circuit including the same, and more particularly, to a delay circuit with reduced layout area and power consumption, and a DLL circuit including the same.
FIG. 1 is a block diagram of a conventional DLL circuit including a duty cycle ratio correction circuit.
As shown, the conventional DLL circuit includes a first delay lock circuit 101, a second delay lock circuit 131, and a duty cycle ratio correction circuit 151.
The first delay lock circuit 101 includes a first phase comparison unit 103, a first delay control unit 105, a first coarse delay unit 107, a first fine delay unit 109, and a first replica model unit 111. The second delay lock unit 131 includes a second phase comparison unit 133, a second delay control unit 135, a second coarse delay unit 137, a second fine delay unit 139, and a second replica model unit 141. The duty cycle ratio correction circuit 151 includes a duty cycle ratio correction unit 153 and a duty cycle ratio detection unit 155.
The first phase comparison unit 103 compares a phase of a first feedback clock FB_1 outputted from the first replica model unit 111 with a phase of an external clock EXT_CLK to thereby generate a first comparison signal CMP_1. The first comparison signal CMP1 contains information about a phase difference between the external clock EXT_CLK and the first feedback clock FB_1. The first replica model unit 111, which is a circuit for modeling a clock delay factor in a semiconductor device, receives a first internal clock OUT_1 of which a duty cycle ratio is corrected by the duty cycle ratio correction unit 153, and then outputs the first feedback clock FB_1. The first comparison signal CMP_1 generated by the first phase comparison unit 103 is inputted to the first delay control unit 105. To match the phases of the external clock EXT_CLK and the first feedback clock FB_1, the first delay control unit 105 generates a first coarse delay control signal DLC_1 and a first fine delay control signal DLF_1 in response to the first comparison signal CMP_1.
The first coarse delay unit 107 delays the external clock EXT_CLK by a coarse delay amount COARSE_DD (delay amount corresponding to two delay units in FIG. 3) to output one of a first coarse delay clock CLKDC_1 and a second coarse delay clock CLKDC_2 in response to the first coarse delay control signal DLC_1. Herein, the first coarse delay unit 107 delays the external clock EXT_CLK such that a time delay between the first and second coarse delay clocks CLKDC_1 and CLKDC_2 is half the coarse delay amount COARSE_DD, i.e., a unit delay amount UNIT_DD (delay amount corresponding to one delay unit in FIG. 3). A difference in delay amount between the first and second coarse delay clocks CLKDC_1 and CLKDC_2 is finely controlled at the first fine delay unit 109.
The first fine delay unit 109 mixes phases of the first and second coarse delay clocks CLKDC_1 and CLKDC_2 in response to the first fine delay control signal DLF_1 so that the external clock EXT_CLK is delayed by a fine delay amount FINE_DD smaller than the unit delay amount UNIT_DD. The first fine delay unit 109 outputs a first delay-locked internal clock CLK_1.
The second delay lock circuit 131 also performs a similar operation to that of the first delay lock circuit 101, and thus matches phase of the external clock EXT_CLK and a second feedback clock FB_2 to output a second delay-locked internal clock CLK_2. However, since the second fine delay lock unit 139 inverts and outputs the external clock EXT_CLK for the duty cycle ratio correction operation to be described later, rising edges of the first and second delay-locked internal clock internal clocks CLK_1 and CLK_2 are in-phase, and a duty cycle ratio of the second delay-locked internal clock CLK_2 is opposite to that of the first delay-locked internal clock CLK_1. The symbol of circlet given to an output terminal of the second fine delay unit 139 in FIG. 1 means ‘inversion’.
The first and second delay-locked internal clocks CLK_1 and CLK_2 are inputted to the duty cycle ratio correction circuit 151. The duty cycle ratio detection unit 155 detects duty cycle ratios of the first and second delay-locked internal clocks CLK_1 and CLK_2 to output a correction signal CTRL_1 corresponding to the duty cycle ratios of the first and second delay-locked internal clocks CLK_1 and CLK_2 to the duty cycle ratio correction unit 153. Since the rising edges of the first and second delay-locked internal clocks CLK_1 and CLK_2 are in-phase with each other, the duty cycle ratio correction unit 153 mixes phases of falling edge of the first and second delay-locked internal clocks CLK_1 and CLK_2 in response to the correction signal CTRL_1, thereby outputting the first and second internal clocks OUT_1 and OUT_2 of which duty cycle ratios are corrected.
FIG. 2 is a block diagram illustrating another conventional DLL circuit including a duty cycle ratio correction circuit.
As shown, the conventional DLL circuit includes a first delay lock circuit 201, a second delay lock circuit 231, and a duty cycle ratio correction circuit 251.
The first delay lock circuit 201 includes a phase comparison unit 203, a first delay control unit 205, a first coarse delay unit 207, a first fine delay unit 209, and a replica model unit 211. The second delay lock circuit 231 includes a second delay control unit 233, a second coarse delay unit 235, and a second fine delay unit 237. The duty cycle ratio correction circuit 251 includes a duty cycle ratio correction unit 253 and a duty cycle ratio detection unit 255.
The first delay lock circuit 201 is similar in operation and configuration to the first delay lock circuit 101 of FIG. 1. However, unlike the second delay lock circuit 131 in FIG. 1, the second delay lock circuit 231 does not include a phase comparison unit and a replica model unit. Instead, the second delay lock circuit 231 delays an external clock EXT_CLK to generate a second delay-locked internal clock CLK_2 in response to a comparison signal CMP and a correction signal CTRL_2 generated by the duty cycle ratio detection unit 255. This allows the duty cycle ratio correction circuit 251 to correct duty cycle ratios of the first and second delay-locked internal clocks CLK_1 and CLK_2.
Since the second delay control unit 233 generates a second coarse delay control signal DLC_2 and a second fine delay control signal DLF_2 in response to the comparison signal CMP, a delay amount of the first delay-locked internal clock CLK_1 is equal to that of the second delay-locked internal clock CLK_2. However, the second fine delay unit 237 inverts and outputs an input signal through its output terminal so that the second delay-locked internal clock CLK_2 is an inverted clock of the first delay-locked internal clock CLK_1
As described above, the second delay control unit 233 generates the second coarse delay control signal DLC_2 and the second fine delay control signal DLF_2 in response to the correction signal CTRL_2. The way the second delay control unit 233 generates the second coarse delay control signal DLC_2 and the second fine delay control signal DLF_2 in response to the correction signal CTRL_2 will be described later together with a correction operation of the duty cycle ratio correction circuit 251.
The duty cycle ratio correction unit 253 generates a correction clock CLK_OUT having a logic high level section corresponding to an interval between a rising edge of the first delay-locked internal clock CLK_1 and a rising edge of the second delay-locked internal clock CLK_2, thereby correcting duty cycle ratios of the first and second delay-locked internal clocks CLK_1 and CLK_2. For example, when a logic high level section of the first delay-locked internal clock CLK_1 is narrower than its logic low level section, a logic high level section of the second delay-locked internal clock CLK_2 is wider than its logic low level section because the second delay-locked internal clock CLK_2 is the inverted clock of the first delay-locked internal clock CLK_1. The rising edge of the first delay-locked internal clock CLK_1 is in-phase with the falling edge of the second delay-locked internal clock CLK_2, and the falling edge of the first delay-locked internal clock CLK_1 is in-phase with the rising edge of the second delay-locked internal clock CLK_2. In this case, therefore, the duty cycle ratio correction unit 253 generates the correction clock CLK_OUT having a logic high level section narrower than a logic low level section.
The duty cycle ratio detection unit 255 detects a duty cycle ratio of the correction clock CLK_OUT to output the correction signal CTRL_2 corresponding to the duty cycle ratio of the correction clock CLK_OUT to the second delay control unit 233.
The second delay control unit 233 activates the second coarse delay control signal DLC_2 and the second fine delay control signal DLF_2 in response to the correction signal CTRL_2 to further delay the second delay-locked internal clock CLK_2. Resultantly, the rising edge of the second delay-locked internal clock CLK_2 is delayed more than the falling edge of the first delay-locked internal clock CLK_1, a logic high level section of the correction clock CLK_OUT is broadened, and finally the duty cycle ratio of the correction clock CLK_OUT approaches to 50:50.
FIG. 3 illustrates the first coarse delay unit 107 and the first fine delay unit 109 shown in FIG. 1.
The first coarse delay unit 107 and the first fine delay unit 109 in FIG. 1 are similar in configuration to the second coarse delay unit 137 and the second fine delay unit 139 in FIG. 1, the first and second coarse delay units 207 and 235 in FIG. 2, and the first and second fine delay units 209 and 237 in FIG. 2. Thus, description will be hereinafter made on the first coarse delay unit 107 and the first fine delay unit 109 shown in FIG. 1.
The first coarse delay unit 107 includes a first delay line 301 and a second delay line 302, each including a plurality of delay units that are enabled in response to the first coarse delay control signal DLC_1. To perform a rapid delay operation, the first coarse delay unit 107 delays the external clock EXT_CLK by the coarse delay amount COARSE_DD larger than the fine delay amount FINE_DD.
The first delay line 301 outputs the first coarse delay clock CLKDC_1 in response to the first coarse delay control signal DLC_1, and the second delay line 302 outputs the second coarse delay clock CLKDC_2 in response to the first coarse delay control signal DLC_1. The first coarse delay control signal DLC_1 is activated in pairs such that a difference in delay time between the first and second coarse delay clocks CLKDC_1 and CLKDC_2 corresponds to the unit delay amount UNIT_DD.
For instance, when the first coarse delay control signal DLC_1<3> and the first coarse delay control signal DLC_1<2> are activated, the external clock EXT_CLK is inputted to the delay units 303 and 309 and delayed while passing through delay units 303, 305, 307, 309 and 311 so that the first coarse delay clocks CLKDC_1 and the second coarse delay clocks CLKDC_2 are outputted. The first coarse delay clock CLKDC_1 is further delayed by the unit delay amount UNIT_DD in comparison with the second coarse delay clock CLKDC_2.
In the first fine delay unit 109, the external clock EXT_CLK is finely delayed by the fine delay amount FINE_DD. The first fine delay unit 109 mixes phases of the first and second coarse delay clocks CLKDC_1 and CLKDC_2 by driving the first and second coarse delay clocks CLKDC_1 and CLKDC_2 with different drive abilities to thereby output the first delay-locked internal clock CLK_1 in response to the first fine delay control signal DLF_1.
The delay line configured with a plurality of delay units in the conventional DLL circuit requires a very large occupation area, and the enabled delay units continue to consume power because the clock is continuously toggling. Moreover, if a delay amount of an output signal of the delay line increases, number of the enabled delay units increases, causing the delay line to consume very large amount of power. However, each of the DLL circuits in FIGS. 1 and 2 includes two coarse delay units of which each is provided with two delay lines. That is, since the conventional DLL circuit includes at least four delay lines necessitating a very large occupation area and consume very large amount of power, the conventional DLL circuit is problematic in that its layout area increases and much power is unnecessarily consumed.